HD64F2168 Datasheet, PDF (508/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figure 15.7 shows the sample flowchart for the operations in master transmit mode.
Start
Initialize IIC
Read BBSY in ICCR
No
BBSY = 0?
Yes
Set MST = 1 and
TRS = 1 in ICCR
Set BBSY =1 and
SCP = 0 in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Read ACKB in ICSR
ACKB = 0?
No
Yes
Transmit mode?
No
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Read ACKB in ICSR
No
End of transmission?
(ACKB = 1?)
Yes
Clear IRIC in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
End
[1] Initialization
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte
(slave address + R/W).
(After writing to ICDR, clear IRIC
continuously.)
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit
transferred from the slave device.
Master receive mode
[9] Set transmit data for the second and
subsequent bytes.
(After writing to ICDR, clear IRIC
immediately.)
[10] Wait for 1 byte to be transmitted.
[11] Determine end of transfer
[12] Stop condition issuance
Figure 15.7 Sample Flowchart for Operations in Master Transmit Mode
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR (ICDRT) write operations, are described below.
Rev. 3.00, 03/04, page 468 of 830