HD64F2168 Datasheet, PDF (332/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

11.5.4 Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
Input capture signal
Figure 11.7 Input Capture Input Signal Timing (Usual Case)
If ICRA to ICRD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (φ). Figure 11.8 shows the timing for this case.
Read cycle of ICRA to ICRD
T1
T2
φ
Input capture
input pin
Input capture signal
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)
Rev. 3.00, 03/04, page 292 of 830