HD64F2168 Datasheet, PDF (490/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Bit Bit Name
Initial
Value R/W
Description
1 IRIC
0
R/(W)*¹ At the end of data transfer in clock synchronous serial
format (rise of the 8th transmit/receive clock)
When a start condition is detected with serial format
selected
When a condition occurs in which the ICDRE or ICDRF
flag is set to 1.
• When a start condition is detected in transmit mode
(when a start condition is detected and the ICDRE flag
is set to 1)
• When transmitting the data in the ICDR register buffer
(when data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1, or data
is transferred from ICDRS to ICDRR in receive mode
and the ICDRF flag is set to 1.)
[Clearing conditions]
• When 0 is written in IRIC after reading IRIC = 1
• When ICDR is accessed by DTC *² (This may not be a
clearing condition. For details, see the description of
the DTC operation on the next page.
Notes: 1. Only 0 can be written to clear the flag to 0.
2. The DTC does not support IIC_4 and IIC_5.
3. If the BBSY bit is written to, the value of the flag is not changed.
Rev. 3.00, 03/04, page 450 of 830