HD64F2168 Datasheet, PDF (552/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
HICR0 and HICR1 are initialized to H'00 by a reset or in hardware standby mode.
• HICR0
R/W
Bit Bit Name Initial Value Slave Host Description
7 LPC3E 0
6 LPC2E 0
5 LPC1E 0
R/W 
R/W 
R/W 
LPC Enable 3 to 1
Enables or disables the LPC interface function.
When the host interface is enabled (at least one of
the three bits is set to 1), processing for data transfer
between the slave processor and the host processor
is performed using pins LAD3 to LAD0, LFRAME,
LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD.
• LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, TWR0 to TWR15, SMIC, KCS, or BT
1: LPC channel 3 operation is enabled
• LPC2E
0: LPC channel 2 operation is disabled
No address (LADR2) matches for IDR2, ODR2, or
STR2
1: LPC channel 2 operation is enabled
• LPC1E
0: LPC channel 1 operation is disabled
No address (LADR1) matches for IDR1, ODR1, or
STR1
1: LPC channel 1 operation is enabled
Rev. 3.00, 03/04, page 512 of 830