HD64F2168 Datasheet, PDF (371/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.9.2 Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T₂ state of a TCNT write cycle as shown in figure
12.14, the write takes priority and the counter is not incremented.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.14 Conflict between TCNT Write and Increment
Rev. 3.00, 03/04, page 331 of 830