HD64F2168 Datasheet, PDF (723/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the
following expression:
φ × 10⁶
Error (%) = {[
] − 1} × 100
(N + 1) × B × 64 × 2^{(2×n − 1)}
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation H'06
• Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response H'06
• Response, H'06, (1 byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 20.22.
Host
Waiting for one-bit period
at the specified bit rate
Setting a new bit rate
H'06 (ACK)
Boot program
Setting a new bit rate
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Setting a new bit rate
Figure 20.22 New Bit-Rate Selection Sequence
Rev. 3.00, 03/04, page 683 of 830