HD64F2168 Datasheet, PDF (304/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB)
DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. The
DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed
in 16-bit units. For details, see section 10.4, Bus Master Interface.
• DADRA
Initial
Bit
Bit Name
Value R/W Description
15 to 2 DA13 to DA0 All 1 R/W D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
fixing DA0 and DA1 to 0. The two data bits are not
compared with UC12 and UC13 of DACNT.
1
CFS
1
R/W Carrier Frequency Select
0: Base cycle = resolution (T) × 64
The range of DA13 to DA0: H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
The range of DA13 to DA0: H'0040 to H'3FFF
0

1
R
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 3.00, 03/04, page 264 of 830