HD64F2168 Datasheet, PDF (526/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

[1] Initialize slave receive mode and wait for slave address reception.
[2] When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
ICDRE flag is set to 1. The slave device drives SCL low from the fall of the 9th transmit
clock until ICDR data is written, to disable the master device to output the next transfer
clock.
[3] After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared
to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1
again. The slave device sequentially sends the data written into ICDRS in accordance with
the clock output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR
register writing to the IRIC flag clearing should be performed continuously. Prevent any
other interrupt processing from being inserted.
[4] The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to
determine whether the transfer operation was performed successfully. When one frame of
data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit
clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS
and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this
slave device drives SCL low from the fall of the 9th transmit clock until data is written to
ICDR.
[5] To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is
cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from
the ICDR register writing to the IRIC flag clearing should be performed continuously.
Prevent any other interrupt processing from being inserted.
Transmit operations can be performed continuously by repeating steps [4] and [5].
[6] Clear the IRIC flag to 0.
[7] To end transmission, clear the ACKE bit in the ICCR register to 0, to clear the acknowledge
bit stored in the ACKB bit to 0.
[8] Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
[9] Dummy-read ICDR to release SCL on the slave side.
[10] When the stop condition is detected, that is, when SDA is changed from low to high when
SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1.
When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it
is cleared to 0.
Rev. 3.00, 03/04, page 486 of 830