HD64F2168 Datasheet, PDF (122/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

5.4 Interrupt Sources
5.4.1 External Interrupts
There are four external interrupts: NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE8.
These interrupts can be used to restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. Interrupts IRQ15 to IRQ0 have the following
features:
• The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an
independent vector address.
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, clear the
corresponding port DDR to 0 so that it is not used as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
IRQnSCA, IRQnSCB
IRQnE
IRQn input or
ExIRQn* input
Edge/level
detection circuit
IRQnF
S
Q
R
Clear signal
IRQn interrupt
request
n = 15 to 0
Note: * ExIRQn stands for ExIRQ15 to ExIRQ2.
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
Rev. 3.00, 03/04, page 82 of 830