HD64F2168 Datasheet, PDF (506/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
SLA
R/W A
DATA
A
DATA
A/A
P
Figure 15.5 I²C Bus Timing
Table 15.8 I²C Bus Data Format Symbols
Symbol
S
SLA
R/W
A
DATA
P
Description
Start condition. The master device drives SDA from high to low while SCL is high
Slave address. The master device selects the slave device.
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
Stop condition. The master device drives SDA from low to high while SCL is high
Rev. 3.00, 03/04, page 466 of 830