HD64F2168 Datasheet, PDF (558/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)
The bits 6 to 0 in HICR2 control interrupts from the LPC interface module to the slave processor
(this LSI). HICR3 and the bit 7 of HICR2 monitor the LPC interface pin states.
Bits 6 to 0 in HICR2 are initialized to H'00 by a reset or in hardware standby mode. The states of
the other bits are determined by the pin states.
The pin states can be monitored regardless of the LPC interface operating state or the operating
state of the functions that use pin multiplexing.
• HICR2
R/W
Bit Bit Name Initial Value Slave Host Description
7 GA20 Undefined R
 GA20 Pin Monitor
6 LRST 0
R/(W)*  LPC Reset Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
an LPC hardware reset occurs.
0: [Clearing condition]
• Writing 0 after reading LRST = 1
1: [Setting condition]
• LRESET pin falling edge detection
5 SDWN 0
R/(W)*  LPC Shutdown Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
an LPC hardware shutdown request is generated.
0: [Clearing conditions]
• Writing 0 after reading SDWN = 1
• LPC hardware reset
• LPC software reset
1: [Setting condition]
• LPCPD pin falling edge detection
Rev. 3.00, 03/04, page 518 of 830