HD64F2168 Datasheet, PDF (148/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.3.3 Wait State Control Register (WSCR)
WSCR is used to specify the data bus width, the number of access states, the wait mode, and the
number of wait states for access to external address spaces (basic extended area and 256-kbyte
extended area). The bus width and the number of access states for internal memory and internal
I/O registers are fixed regardless of the WSCR settings.
Initial
Bit Bit Name Value R/W Description
7 ABW256 1
R/W 256-kbyte Extended Area Bus Width Control
Selects the bus width for access to the 256-kbyte extended
area when the CS256E bit in SYSCR is set to 1.
0: 16-bit bus
1: 8-bit bus
6 AST256 1
R/W 256-kbyte Extended Area Access State Control
Selects the number of states for access to the 256-kbyte
extended area when the CS256E bit in SYSCR is set to 1.
This bit also enables or disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled
5 ABW
1
R/W Basic Extended Area Bus Width Control
Selects the bus width for access to the basic extended area.
0: 16-bit bus
1: 8-bit bus
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
Rev. 3.00, 03/04, page 108 of 830