HD64F2168 Datasheet, PDF (197/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

7.2.10 Event Counter Control Register (ECCR)
ECCR selects the event counter channels for use and the detection edge.
Initial
Bit
Bit Name Value
7
EDSB
0
6 to 4 —
All 0
3 to 0 ECSB3 to All 0
ECSB0
R/W Description
R/W Event Counter Edge Select
Selects the detection edge for the event counter.
0: Counts the rising edges
1: Counts the falling edges
R
Reserved
These bits are always read as 0 and cannot be
modified.
R/W Event Counter Channel Select 3 to 0
These bits select pins for event counter input. A series
of pins are selected starting from EVENT0. When
PAnDDR is set to 1, inputting events to EVENT0 to
EVENT7 is ignored.
0000: EVENT0 is used
0001: EVENT0 to EVENT1 are used
0010: EVENT0 to EVENT2 are used
0011: EVENT0 to EVENT3 are used
0100: EVENT0 to EVENT4 are used
0101: EVENT0 to EVENT5 are used
0110: EVENT0 to EVENT6 are used
0111: EVENT0 to EVENT7 are used
1000: EVENT0 to EVENT8 are used
1001: EVENT0 to EVENT9 are used
1010: EVENT0 to EVENT10 are used
1011: EVENT0 to EVENT11 are used
1100: EVENT0 to EVENT12 are used
1101: EVENT0 to EVENT13 are used
1110: EVENT0 to EVENT14 are used
1111: EVENT0 to EVENT15 are used
Rev. 3.00, 03/04, page 157 of 830