HD64F2168 Datasheet, PDF (843/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 25.10 Timing of On-Chip Peripheral Modules
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 5 MHz to 33 MHz
Item
Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time
Input data setup time
Input data hold time
FRT
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Single edge
Both edges
TMR Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
Single edge
Both edges
PWM, Timer output delay time
PWMX
t_PWD
t
PRS
t
PRH
t
FTOD
t
FTIS
t_FTCS
t_FTCWH
t_FTCWL
t_TMOD
t_TMRS
t
TMCS
t
TMCWH
t
TMCWL
t
PWOD
 30 ns Figure 25.19
20 
20 
 30 ns Figure 25.20
20 
20 
Figure 25.21
1.5 
t_cyc
2.5 
 30 ns Figure 25.22
20 
Figure 25.24
20 
Figure 25.23
1.5 
t
cyc
2.5 
 30 ns Figure 25.25
SCI
Input clock cycle Asynchronous t_Scyc
Synchronous
4
 t_cyc Figure 25.26
6

Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
(synchronous)
t_SCKW
t_SCKr
t
SCKf
t
TXD
0.4 0.6 t_Scyc

1.5 t_cyc
 1.5
 30 ns Figure 25.27
Receive data setup time
(synchronous)
t
RXS
20 
Receive data hold time
(synchronous)
t_RXH
20 
A/D
Trigger input setup time
converter
t_TRGS
20  ns Figure 25.28
WDT RESO output delay time
t
RESD
 200 ns Figure 25.29
RESO output pulse width
t
RESOW
132 
t
cyc
Note: * Only the peripheral modules that can be used in subclock operation.
Rev. 3.00, 03/04, page 803 of 830