HD64F2168 Datasheet, PDF (589/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
7 to 5 
All 0
R/W  Reserved
The initial value should not be changed.
4 HDTWI 0
R/(W)*  Transfer Data Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the transfer data to SMICDTR.
When the IBFIE3 bit and HDTWIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data transmission wait state
[Clearing condition]
After the slave reads HDTWI = 1, writes 0 to this bit.
1: Transfer data transmission end
[Setting condition]
The transfer cycle is write transfer and the host
writes the transfer data to SMICDTR.
3 HDTRI 0
R/(W)*  Transfer Data Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the transfer data from SMICDTR.
When the IBFIE3 bit and HDTRIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data receive wait state
[Clearing condition]
After the slave reads HDTRI = 1, writes 0 to this bit.
1: Transfer data receive end
[Setting condition]
The transfer cycle is read transfer and the host
reads the transfer data from SMICDTR.
2 STARI 0
R/(W)*  Status Code Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the status code from SMICCSR.
When the IBFIE3 bit and STARIE bit are set to 1, the
IBFI3 interrupt is requested to the slave.
0: Status code receive wait state
[Clearing condition]
After the slave reads STARI = 1, writes 0 to this bit.
1: Status code receive end
[Setting condition]
When the host reads the status code of SMICCSR.
Rev. 3.00, 03/04, page 549 of 830