HD64F2168 Datasheet, PDF (624/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.5 Interrupt Sources
16.5.1 IBFI1, IBFI2, IBFI3, ERRI
The LPC interface has four interrupt requests to the slave processor: IBFI1, IBFI2, IBFI3, and
ERRI. IBFI1 and IBFI2 are receive complete interrupts for IDR1 and IDR2 respectively. IBFI3 is
a receive complete interrupt for IDR3 and TWR, and the interrupt in SMIC mode and BT mode.
The ERRI interrupt indicates the occurrence of a special state, such as an LPC reset, LPC
shutdown, or transfer cycle abort. An interrupt request is enabled by setting the corresponding
enable bit.
Table 16.11 Receive Complete Interrupts and Error Interrupt
Interrupt
IBFI1
IBFI2
IBFI3
ERRI
Description
Requested when IBFIE1 is set to 1 and IDR1 reception is completed
Requested when IBFIE2 is set to 1 and IDR2 reception is completed
Requested when IBFIE3 is set to 1 and IDR3 reception is completed, or when
TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15
Interrupts by HDTWI, HDTRI, STARI, CTLWI, and BUSYI of SMIC mode
Interrupts by FRDI, HRDI, HWRI, HBTWI, HBTRI, HRSTI, IRQCRI, BEVTI, B2HI,
H2BI, CRRPI, and CRWPI of BT mode
Requested when ERRIE is set to 1 and LRST, SDWN, or ABRT is set to 1
16.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12
The LPC interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can
be requested from LPC channel 2 or 3.
There are two ways of clearing a host interrupt request.
When the IEDIR bit in SIRQCR0 and the IEDIR3 bit in SIRQCR2 are cleared to 0s, host interrupt
sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF
flag is cleared to 0 by a read by the host of ODR or TWR15 in the corresponding LPC channel, the
corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request
is cleared.
When the IEDIR bit in SIRQCR0 and the IEDIR3 bit in SIRQCR2 are set to 1s, LPC channel 2
and 3 interrupt requests are dependent only upon the host interrupt enable bits. The host interrupt
enable bit is not cleared when OBF for channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and
SMIE3B, IRQ6E2 and IRQ6E3, IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2
and IRQ11E3 lose their respective functional differences when both bits IEDIR and IEDIR3 are
Rev. 3.00, 03/04, page 584 of 830