HD64F2168 Datasheet, PDF (95/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

3.2.2 System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, enables or disables register access to the on-chip peripheral
modules, and enables or disables on-chip RAM address space.
Bit Bit Name Initial Value R/W Description
7 CS256E 0
R/W Chip Select 256 Enable
Enables or disables P97/WAIT/CS256 pin function in
extended mode.
0: P97/WAIT pin
WAIT pin function is selected by the settings of
WSCR and WSCR2.
1: CS256 pin
Outputs low when a 256-kbyte expansion area of
addresses H'F80000 to H'FBFFFF is accessed.
6 IOSE
0
R/W IOS Enable
Enables or disables AS/IOS pin function in extended
mode.
0: AS pin
Outputs low when an external area is accessed.
1: IOS pin
Outputs low when an IOS expansion area of
addresses H'FFF000 to H'FFF7FF is accessed.
5 INTM1
0
4 INTM0
0
R
These bits select the control mode of the interrupt
R/W controller. For details on the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
3 XRST
1
R
External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
2 NMIEG
0
R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Rev. 3.00, 03/04, page 55 of 830