HD64F2168 Datasheet, PDF (416/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2)
SEMR_0 and SEMR_2 select the SCI_0 and SCI_2 functions, respectively, and the clock source
in asynchronous mode. The basic clock is automatically specified when the average transfer rate
operation is selected.
Bit Bit Name Initial Value R/W Description
7
SSE
0
R/W SCI Select Enable
Enables/disables the external pins to select the SCI
functions when the external clock is supplied in clock
synchronous mode.
0: Disables the external pins to select the SCI functions
(normal)
1: Enables the external pins to select the SCI functions
• SCI_0
SSE0I pin input = 0 (selected state): SCI_0 operates
normally
SSE0I pin input = 1 (non-selected state): SCI_0 halts
operation
(TxD0 = high-impedance state, SCK0 = fixed to high)
• SCI_2
SSE2I pin input = 0 (selected state): SCI_2 operates
normally
SSE2I pin input = 1 (non-selected state): SCI_2 halts
operation
(TxD2 = high-impedance state, SCK2 = fixed to high)
6, 5 
All 0
R Reserved
These bits are always read as 0 and cannot be
modified.
3
ABCS
0
R/W Asynchronous Mode Basic Clock Select
Specifies the basic clock for a 1-bit cycle in
asynchronous mode.
This bit is valid only in asynchronous mode (C/A bit in
SMR is 0).
0: The basic clock has a frequency 16 times the transfer
clock frequency (normal operation)
1: The basic clock has a frequency 8 times the transfer
clock frequency (double-speed operation)
Rev. 3.00, 03/04, page 376 of 830