HD64F2168 Datasheet, PDF (423/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.4.3 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.5.
SCK
TxD
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 14.5 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)
14.4.4 Serial Enhanced Mode Clock
SCI_0 and SCI_2 can be operated not only based on the clocks described in section 14.4.3, Clock,
but based on the following clocks, which are specified by the serial enhanced mode registers,
SEMR_0 and SEMR_2.
Double-Speed Operation: Operations that are usually achieved using the clock with frequency 16
times the normal bit rate can be achieved using the clock with frequency 8 times the bit rate in this
mode. That is, double transfer rate can be achieved using a single basic clock.
Double-speed operation can be specified by the ABCS bit in SEMR and is available for both clock
sources of an internal clock generated by the on-chip baud rate generator and an external clock
input at the SCK pin. However, double-speed operation cannot be specified when the average
transfer rate operation is selected.
Average Transfer Rate Operation: The SCI can be operated based on the clock with an average
transfer rate generated from the system clock instead of the external clock input at the SCK pin. In
this case, the SCK pin is fixed to input.
Average transfer rate operation can be specified by the ACS4 and ACS2 to ACS0 bits in SEMR.
Double-speed operation may be selected by clearing the ACS4 and ACS2 to ACS0 bits to 0.
Figures 14.6 and 14.7 show some examples of internal basic clock operations when average
transfer rate operation is selected.
Rev. 3.00, 03/04, page 383 of 830