HD64F2168 Datasheet, PDF (608/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

If the received address matches the host address in an LPC register, the LPC interface enters the
busy state; it returns to the idle state by output of a state #12 turnaround. Register (IDR, etc.) and
flag (IBF, etc.) changes are made at this timing, so in the event of a transfer cycle forced
termination (abort) before state #12, registers and flags are not changed.
Table 16.5 I/O Read and Write Cycles
I/O Read Cycle
State
Count Contents
Drive Value
Source (3 to 0)
1
Start
Host B'0000
2
Cycle type/direction Host B'0000
3
Address 1
Host
Bits 15 to
12
4
Address 2
Host Bits 11 to 8
5
Address 3
Host Bits 7 to 4
6
Address 4
Host Bits 3 to 0
7
Turnaround
(recovery)
Host B'1111
8
Turnaround
None B'ZZZZ
9
Synchronization Slave B'0000
10
Data 1
11
Data 2
12
Turnaround
(recovery)
13
Turnaround
Slave
Slave
Slave
Bits 3 to 0
Bits 7 to 4
B'1111
None B'ZZZZ
I/O Write Cycle
Contents
Drive Value
Source (3 to 0)
Start
Host B'0000
Cycle type/direction Host B'0010
Address 1
Host
Bits 15 to
12
Address 2
Host Bits 11 to 8
Address 3
Host Bits 7 to 4
Address 4
Host Bits 3 to 0
Data 1
Host Bits 3 to 0
Data 2
Turnaround
(recovery)
Turnaround
Synchronization
Turnaround
(recovery)
Turnaround
Host
Host
Bits 7 to 4
B'1111
None
Slave
Slave
B'ZZZZ
B'0000
B'1111
None B'ZZZZ
Rev. 3.00, 03/04, page 568 of 830