HD64F2168 Datasheet, PDF (125/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

5.5 Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting are
given priority and processed before interrupt requests from modules that are set to interrupt control
level 0 (no priority).
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Name
External pin NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
DTC
SWDTEND (Software activation
data transfer end)
WDT_0
WOVI0 (Interval timer)
WDT_1
WOVI1 (Interval timer)
—
Address break
A/D converter ADI (A/D conversion end)
EVC
EVENTI
External pin
KIN7 to KIN0
KIN15 and KIN8
WUE15 to WUE8
TMR_X
CMIAX (Compare match A)
CMIBX (Compare match B)
OVIX (Overflow)
ICIX (Input capture)
Vector Address
Vector
Number Advanced Mode ICR
7
H'00001C
—
16
H'000040
ICRA7
17
H'000044
ICRA6
18
H'000048
19
H'00004C
ICRA5
20
H'000050
21
H'000054
ICRA4
22
H'000058
23
H'00005C
ICRA3
24
H'000060
ICRA2
25
H'000064
26
H'000068
27
H'00006C
28
H'000070
29
H'000074
30
H'000078
31
H'00007C
33
H'000084
44
H'0000B0
45
H'0000B4
46
H'0000B8
47
H'0000BC
ICRA1
ICRA0
—
ICRB7
—
—
ICRB4
Priority
High
Low
Rev. 3.00, 03/04, page 85 of 830