HD64F2168 Datasheet, PDF (597/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.21 BT Control Status Register 0 (BTCSR0)
BTCSR0 is one of the registers used to implement the BT mode. The BTCSR0 register contains
the bits used to switch FIFOs in BT transfer, and enable or disable the interrupts to the slave (this
LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1.
R/W
Bit Bit Name Initial Value Slave Host Description
7
0
R/W  Reserved
The initial value should not be changed.
6 FSEL1 0
5 FSEL0 0
R/W 
R/W 
These bits select either FIFO during BT transfer
FSEL1 FSEL0
0
* :FIFO disabled
1
* :FIFO enabled
The FIFO size: 64 bytes (for host write transfer),
additional 64 bytes (for host read transfer).
4 FRDIE 0
R/W  FIFO Read Request Interrupt Enable
Enables or disables the FRDI interrupt which is an
IBFI3 interrupt source to the slave.
0: FIFO read request interrupt is disabled.
1: FIFO read request interrupt is enabled.
3 HRDIE 0
R/W  BT Host Read Interrupt Enable
Enables or disables the HRDI interrupt which is an
IBFI3 interrupt source to the slave.
When using FIFO, the HRDIE bit must not be set to 1.
0: BT host read interrupt is disabled.
1: BT host read interrupt is enabled.
2 HWRIE 0
R/W  BT Host Write Interrupt Enable
Enables or disables the HWRI interrupt which is an
IBFI3 interrupt source to the slave.
When using FIFO, the HWRIE bit must not be set to
1.
0: BT host write interrupt is disabled.
1: BT host write interrupt is enabled.
Rev. 3.00, 03/04, page 557 of 830