HD64F2168 Datasheet, PDF (509/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

[1] Initialize the IIC as described in section 15.4.2, Initialization.
[2] Read the BBSY flag in ICCR to confirm that the bus is free.
[3] Set bits MST and TRS to 1 in ICCR to select master transmit mode.
[4] Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
high, and generates the start condition.
[5] Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU.
[6] Write the data (slave address + R/W) to ICDR.
With the I²C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first
frame data following the start condition indicates the 7-bit slave address and transmit/receive
direction (R/W).
To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR,
clear IRIC continuously so no other interrupt handling routine is executed. If the time for
transmission of one frame of data has passed before the IRIC clearing, the end of
transmission cannot be determined. The master device sequentially sends the transmission
clock and the data written to ICDR. The selected slave device (i.e. the slave device with the
matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge signal.
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[8] Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device
has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the
transmit operation.
[9] Write the transmit data to ICDR.
As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write
and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is
performed in synchronization with the internal clock.
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[11] Read the ACKB bit in ICSR.
Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still
data to be transmitted, go to step [9] to continue the next transmission operation. When the
slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end
transmission.
[12] Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP
in ICCR. This changes SDA from low to high when SCL is high, and generates the stop
condition.
Rev. 3.00, 03/04, page 469 of 830