HD64F2168 Datasheet, PDF (562/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.4 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
• LADR3H
R/W
Bit Bit Name Initial Value Slave Host
7 Bit 15 All 0
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
0 Bit 8
R/W 
Description
Channel 3 Address Bits 15 to 8
The host address of LPC channel 3 is set.
• LADR3L
R/W
Bit Bit Name Initial Value Slave Host
7 Bit 7
All 0
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
R/W 
2
0
R/W 
1 Bit 1
0
R/W 
0 TWRE 0
R/W 
Description
Channel 3 Address Bits 7 to 3
The host address of LPC channel 3 is set.
Reserved
The initial value should not be changed.
Channel 3 Address Bit 1
The host address of LPC channel 3 is set.
Bidirectional data Register Enable
Enables or disables bidirectional data register
operation.
Clear this bit to 0 in KCS mode.
0: TWR operation is disabled
TWR-related address (LADR3) match does not
occur.
1: TWR operation is enabled
Rev. 3.00, 03/04, page 522 of 830