HD64F2168 Datasheet, PDF (520/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

The reception procedure and operations using the HNDS bit function by which data reception
process is provided in 1-byte unit with SCL being fixed low at every data reception, are described
below.
[1] Initialize the IIC as described in section 15.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and
the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
[2] Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
[3] When the start condition output by the master device is detected, the BBSY flag in ICCR is
set to 1. The master device then outputs the 7-bit slave address, and transmit/receive
direction (R/W), in synchronization with the transmit clock pulses.
[4] When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
[5] At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as the acknowledge data.
[6] At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, IRTR flag is also set to 1.
[7] At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive
clock pulse until data is read from ICDR.
[8] Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0.
[9] If the next frame is the last receive frame, set the ACKB bit to 1.
[10] If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the
master device to transfer the next data.
Receive operations can be performed continuously by repeating steps [5] to [10].
[11] When the stop condition is detected (SDA is changed from low to high when SCL is high),
the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been
cleared to 0, the IRIC flag is set to 1.
[12] Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
Rev. 3.00, 03/04, page 480 of 830