HD64F2168 Datasheet, PDF (685/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the dummy data to be added is H'FF, the program processing period can be
shortened.
1. Select the on-chip program to be downloaded and specify a download destination
When the PPVS bit of FPCS is set to 1, the programming program is selected. Several
programming/erasing programs cannot be selected at one time. If several programs are set,
download is not performed and a download error is returned to the SS bit in DPFR. The start
address of a download destination is specified by FTDAR.
2. Program H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be set to the SCO bit for download
request.
3. 1 is set to the SCO bit of FCCS and then download is executed.
To set 1 to the SCO bit, the following conditions must be satisfied.
 H'A5 is written to FKEY.
 The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned
to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of DPFR. Before the SCO bit is
set to 1, incorrect determination must be prevented by setting the one byte of the start address
(to be used as DPFR) specified by FTDAR to a value other than the return value (e.g. H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing. Four NOP
instructions are executed immediately after the instructions that set the SCO bit to 1.
 The user-MAT space is switched to the on-chip program storage area.
 After the selection condition of the download program and the FTDAR setting are checked,
the transfer processing to the on-chip RAM specified by FTDAR is executed.
 The SCO bit in FCCS is cleared to 0.
 The return value is set to the DPFR parameter.
 After the on-chip program storage area is returned to the user-MAT space, the user
procedure program is returned.
 In the download processing, the values of general registers of the CPU are held.
Rev. 3.00, 03/04, page 645 of 830