HD64F2168 Datasheet, PDF (186/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

φ
Address bus
Full access
T₁
T₂
Burst access
T₁
T₁
Only lower
address changes
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Read data Read data
Figure 6.28 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2 Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is
possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.5,
Wait Control. Wait states cannot be inserted in a burst cycle.
Rev. 3.00, 03/04, page 146 of 830