HD64F2168 Datasheet, PDF (563/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are ignored. When determining an IDR3,
ODR3, or STR3 address match in KCS mode, an SMICFLG, SMICCSR, SMICDTR address
match in SMIC mode, and a BTDTR, BTCR, BTIMSR address match in BT mode, the values of
bits 3 to 0 are ignored.
Register selection according to the bits ignored in address match determination is as shown in the
following table.
Bits 15 to5
Bits 15 to5
Bits 15 to5
Bits 15 to5
Bits 15 to5
Bits 15 to5
Bits 15 to5
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bits 15 to5 Bit 4
Bits 15 to5 Bit 4
I/O Address
Bit 3 Bit 2
Bit 3 0
Bit 3 1
Bit 3 0
Bit 3 1
0
0
0
0
•
•
•
•
•
•
1
1
0
0
0
0
•
•
•
•
•
•
1
1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
0
0
•
•
•
1
0
0
•
•
•
1
Bit 0
0
0
0
0
0
1
•
•
•
1
0
1
•
•
•
1
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
I/O write
I/O write
Host Register
Selection
IDR3 write, C/D3 ← 0
IDR3 write, C/D3 ← 1
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15
write
I/O read
I/O read
TWR0SW read
TWR1 to TWR15
read
Rev. 3.00, 03/04, page 523 of 830