HD64F2168 Datasheet, PDF (212/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 7.9 Number of States Required for Each Execution Status
Object to be Accessed
On-Chip RAM
On-Chip RAM (On-chip RAM area
On-
(H'FFEC00 to other than H'FFEC00 to Chip
H'FFEFFF)
H'FFEFFF)
ROM
Bus width
32
16
16
Access states
1
1
1
Execution Vector read S —
—
1
I
status
Register
1
—
—
information
read/write S
J
Byte data read S 1
1
1
K
Word data read 1
1
1
S
K
Byte data write S 1
1
1
L
Word data write 1
1
1
S_L
Internal operation 1
1
1
S_M
On-Chip
I/O
Registers
External Devices
8 16 8 8
16
2223
2
— — 4 6 + 2m 2
————
—
2 2 2 3+m 2
4 2 4 6 + 2m 2
2 2 2 3+m 2
4 2 4 6 + 2m 2
1111
1
16
3
3+m
—
3+m
3+m
3+m
3+m
1
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Rev. 3.00, 03/04, page 172 of 830