HD64F2168 Datasheet, PDF (391/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface
(SCI, IrDA, and CRC)
This LSI has three independent serial communication interface (SCI) channels. The SCI can
handle both asynchronous and clock synchronous serial communication. Asynchronous serial data
communication can be carried out with standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function). The SCI also supports the smart card (IC
card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous
communication function.
SCI_1 can handle communication using the waveform based on the Infrared Data Association
(IrDA) standard version 1.0. SCI_0 and SCI_2 provide high-speed communication at an average
transfer rate of a specific system clock frequency. Reliable fast data transfers are secured using the
internal cyclic redundancy check (CRC) operation circuit. Since the CRC operation circuit is not
connected to the SCI, data is transferred to the circuit using the MOV instruction to be operated
there.
14.1 Features
• Choice of asynchronous or clock synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
The external clock can be selected as a transfer clock source (except for the smart card
interface).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources  transmit-end, transmit-data-empty, receive-data-full, and receive
error  that can issue requests.
The transmit-data-empty and receive-data-full interrupt sources can activate DTC.
• Module stop mode availability
SCI0022A_000120020900
Rev. 3.00, 03/04, page 351 of 830