HD64F2168 Datasheet, PDF (771/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Bit Bit Name
6 LSON
5 NESEL
4 EXCLE
3
2 PNCCS
1 PNCAH
Initial
Value
0
0
0
0
0
0
R/W Description
R/W Low-Speed On Flag
Specifies the operating mode to be entered after executing the
SLEEP instruction. This bit also controls whether to shift to high-
speed mode or subactive mode when watch mode is cancelled.
When the SLEEP instruction is executed in high-speed mode or
medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch mode
1: Shifts to watch mode or subactive mode
When the SLEEP instruction is executed in subactive mode:
0: Shifts directly to watch mode or high-speed mode
1: Shifts to subsleep mode or watch mode
When watch mode is cancelled:
0: Shifts to high-speed mode
1: Shifts to subactive mode
R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB) input from
the EXCL pin is sampled using the clock (φ) generated by the
system clock pulse generator.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
R/W Reserved
The initial value should not be changed.
R/W Address Multiplex Chip Select
Controls the output polarity of chip select signals (CS256, CPCS,
IOS) in the address multiplex extended mode.
0: Outputs CS256, CPCS, and IOS
1: Outputs CS256, CPCS, and IOS
R/W Address Multiplex Address Hold
Controls the output polarity of the address hold signal (AH) in the
address multiplex extended mode.
0: Outputs AH
1: Outputs AH
Rev. 3.00, 03/04, page 731 of 830