HD64F2168 Datasheet, PDF (567/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 16.4 Slave Selection Internal Registers
Slave (R/W) Bus Width (B/W) LADR12SEL
LADR12
R/W
B
0
LADR12H
R/W
B
1
LADR12H
R/W
B
0
LADR12L
R/W
B
1
LADR12L
R/W
W
0
LADR12H LADR12L
R/W
W
1
LADR12H LADR12L
Internal Register
LADR1H
LADR2H
LADR1L
LADR2L
LADR1H LADR1L
LADR2H LADR2L
16.3.6 Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit write-
only registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on IDR1 and IDR2 selection, see
section 16.3.5, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on IDR3 selection, see section 16.3.4, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). Data transferred in an LPC I/O write cycle is written to the selected
register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether
the written information is a command or data.
The initial values of the IDR registers are undefined.
16.3.7 Output Data Registers 0 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers to the slave processor (this LSI), and 8-bit
read-only registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on ODR1 and ODR2 selection, see
section 16.3.5, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on ODR3 selection, see section 16.3.4, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). In an LPC I/O read cycle, the data in the selected register is transferred to
the host.
The initial values of the ODR registers are undefined.
Rev. 3.00, 03/04, page 527 of 830