HD64F2168 Datasheet, PDF (511/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.4.4 Master Receive Operation
In I²C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 15.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 1 in ICXR
Clear IRIC in ICCR
Last receive? ^Yes
No
Read ICDR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR
[1] Select receive mode.
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock for the receive frame)
[4] Clear IRIC.
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR
Set TRS = 1 in ICCR
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
End
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
Dummy read to start receiving if the first frame is
the last receive data.
[8] Wait for 1 byte to be received.
[9] Clear IRIC.
[10] Read the receive data.
[11] Set stop condition issuance.
Generate stop condition.
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
Rev. 3.00, 03/04, page 471 of 830