HD64F2168 Datasheet, PDF (386/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

13.4.3 RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 13.5.
φ
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
H'FF
H'00
132 states
Internal reset
signal
518 states
Figure 13.5 Output Timing of RESO signal
Rev. 3.00, 03/04, page 346 of 830