HD64F2168 Datasheet, PDF (586/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.14 SMIC Flag Register (SMICFLG)
SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that
indicate whether or not the system is ready to data transfer and those that are used for handshake
of the transfer cycles.
R/W
Bit Bit Name Initial Value Slave Host Description
7 RX_DATA_ 0
RDY
R/W R
Read Transfer Ready
Indicates whether or not the slave is ready for the
host read transfer.
0: Slave waits for ready status
1: Slave is ready for the host read transfer
6 TX_DATA_ 0
RDY
R/W R
Write Transfer Ready
Indicates whether or not the slave is ready for the
host next write transfer.
0: The slave waits for ready status
1: The slave is ready for the host write transfer.
5
0
R/W R Reserved
The initial value should not be changed.
4 SMI
0
R/W R SMI Flag
This bit indicates that the SMI is asserted.
0: Indicates waiting for SMI assertion
1: Indicates SMI assertion
Rev. 3.00, 03/04, page 546 of 830