HD64F2168 Datasheet, PDF (305/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

• DADRB
Initial
Bit Bit Name Value
15 to 2 DA13 to DA0 All 1
1
CFS
1
0
REGS
1
R/W Description
R/W D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
fixing DA0 and DA1 to 0. The two data bits are not
compared with UC12 and UC13 of DACNT.
R/W Carrier Frequency Select
0: Base cycle = resolution (T) × 64
DA13 to DA0 range = H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
DA13 to DA0 range = H'0040 to H'3FFF
R/W Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed. When changing the
register to be accessed, set this bit in advance.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 3.00, 03/04, page 265 of 830