HD64F2168 Datasheet, PDF (111/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
5.1 Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
• Priorities settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels
can be set for each module for all interrupts except NMI, KIN, and WUE.
• Three-level interrupt mask control
By means of the interrupt control mode, I and UI bits in CCR, and ICR, 3-level interrupt mask
control is performed.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Forty-one external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for IRQ15 to IRQ0. An interrupt is requested at the falling edge for
KIN15 to KIN0 and WUE15 to WUE8.
• DTC control
The DTC can be activated by an interrupt request.
Rev. 3.00, 03/04, page 71 of 830