HD64F2168 Datasheet, PDF (482/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

• I²C bus format: addressing format with acknowledge bit
• Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master mode only
15.3.4 I²C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Initial
Bit Bit Name Value
7
MLS
0
6
WAIT
0
5
CKS2
All 0
4
CKS1
3
CKS0
R/W Description
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
R/W Wait Insertion Bit
This bit is valid only in master mode with the I²C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8th clock),
the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is
cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
For details, refer to section 15.4.7, IRC Setting Timing and
SCL Control.
R/W Transfer Clock Select
These bits are used only in master mode.
These bits select the required transfer rate, together with
the IICX5 (channel 5), IICX4 (channel 4), and IICX3
(channel 3) bits in IICX3, and the IICX2 (channel 2), IICX1
(channel 1), and IICX0 (channel 0) bits in STCR. Refer to
table 15.3.
Rev. 3.00, 03/04, page 442 of 830