HD64F2168 Datasheet, PDF (351/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.3.4 Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
TCR_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS
is 1. TCR_X can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section 12.3.11, Timer
Connection Register S (TCONRS).
Bit
7
6
5
4
3
2 to 0
Bit Name Initial Value R/W Description
CMIEB 0
R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
CMIEA 0
R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
OVIE
0
R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
CCLR1 0
CCLR0 0
R/W Counter Clear 1 and 0
R/W _{These bits select the method by which the timer}
counter is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
CKS2 to All 0
CKS0
R/W Clock Select 2 to 0
These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
STCR. For details, see table 12.2.
Rev. 3.00, 03/04, page 311 of 830