HD64F2168 Datasheet, PDF (515/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Read ICDR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Set WAIT = 0 in ICMR
Clear IRIC in ICCR
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
[1] Select receive mode.
[2] Start receiving. The first read
is a dummy read.
[3] Wait for a receive wait
(Set IRIC at the fall of the 8 th clock)
[7] Set acknowledge data for
the last reception.
[9] Set TRS for stop condition issuance
[14] Clear IRIC.
(to end the wait insertion)
[12] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock)
[15] Clear wait mode.
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)
[16] Read the last receive data
[17] Generate stop condition
End
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1)
The reception procedure and operations using the wait function (WAIT bit), by which data is
sequentially received in synchronization with ICDR (ICDRR) read operations, are described
below.
The following describes the multiple-byte reception procedure. In single-byte reception, some
steps of the following procedure are omitted. At this time, follow the procedure shown in figure
15.14
Rev. 3.00, 03/04, page 475 of 830