HD64F2168 Datasheet, PDF (575/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
1 IBF3A 0
R
R Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This bit is an internal interrupt source to the
slave processor (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave processor reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host processor writes to IDR3 using I/O
write cycle
0 OBF3A 0
R/(W)* R Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not receive data in ODR3
[Clearing condition]
When the host processor reads ODR3 using I/O
read cycle, or the slave processor writes 0 to the
OBF3A bit
1: There is receive data in ODR3
[Setting condition]
When the slave processor writes to ODR3
Note: * Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 535 of 830