HD64F2168 Datasheet, PDF (455/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Start
Initialization
Start reception
ORER = 0
No
and PER = 0?
Yes
No
RDRF = 1?
Yes
Read data from RDR and
clear RDRF flag in SSR to 0
Error processing
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 14.33 Sample Reception Flowchart
14.7.8 Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 14.34 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 14.34 Clock Output Fixing Timing
Rev. 3.00, 03/04, page 415 of 830