HD64F2168 Datasheet, PDF (71/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

2.6 Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
POP*¹, PUSH*¹
LDM, STM*²
MOVFPE*³, MOVTPE*³
B/W/L 5
W/L
L
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
B/W/L 19
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS
B
Logic operations AND, OR, XOR, NOT
B/W/L 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
B_CC*⁴, JMP, BSR, JSR, RTS
–
5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, –
9
NOP
Block data transfer EEPMOV
–
1
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot
be used as an STM/LDM register.
3. Cannot be used in this LSI.
4. B is the general name for conditional branch instructions.
CC
Rev. 3.00, 03/04, page 31 of 830