HD64F2168 Datasheet, PDF (435/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.5.1 Multiprocessor Serial Data Transmission
Figure 14.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Initialization
Start transmission
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
Clear DR to 0 and set DDR to 1
[1] [1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
[2]
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
[3]
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to 0.
However, the TDRE flag is
checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
[4]
transmission, set port DDR to 1,
clear DR to 0, and then clear the
TE bit in SCR to 0.
Clear TE bit in SCR to 0
<End>
Figure 14.14 Sample Multiprocessor Serial Transmission Flowchart
Rev. 3.00, 03/04, page 395 of 830