HD64F2168 Datasheet, PDF (437/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Initialization
[1]
Start reception
Set MPIE bit in SCR to 1
[2]
Read ORER and FER flags in SSR
Yes
FER ∨ ORER = 1
No
Read RDRF flag in SSR
[3]
No
RDRF = 1
Yes
Read receive data in RDR
No
This station’s ID?
Yes
Read ORER and FER flags in SSR
Yes
FER ∨ ORER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
Yes
Read receive data in RDR
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
[4]
value.
Legend
∨ : Logical add (OR)
No
All data received?
[5]
Yes
Clear RE bit in SCR to 0
Error processing
(Continued on
next page)
<End>
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 3.00, 03/04, page 397 of 830