HD64F2168 Datasheet, PDF (768/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

23.1 Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be
cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
• Standby control register (SBYCR)
• Low power control register (LPWRCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
• Module stop control register A (MSTPCRA)
• Sub-chip module stop control register BH, BL (SUBMSTPBH, SUBMSTPBL)
• Sub-chip module stop control register AH, AL (SUBMSTPAH, SUBMSTPAL)
23.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name Initial Value R/W Description
7 SSBY 0
R/W Software Standby
Specifies the operating mode to be entered after executing
the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode, subactive mode, or
watch mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode
1: Shifts to watch mode or high-speed mode
Note that the SSBY bit is not changed even if a mode
transition occurs by an interrupt.
Rev. 3.00, 03/04, page 728 of 830