HD64F2168 Datasheet, PDF (672/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

(b) Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the initialization result.
Initial
Bit
Bit Name Value R/W Description
7 to 2 


Unused
Return 0
1
FQ

R/W Frequency Error Detect
Returns the check result whether the specified operating
frequency of the CPU is in the range of the supported
operating frequency.
0: Setting of operating frequency is normal
1: Setting of operating frequency is abnormal
0
SF

R/W Success/Fail
Indicates whether initialization is completed normally.
0: Initialization is ended normally (no error)
1: Initialization is ended abnormally (error occurs)
(3) Programming Execution
When flash memory is programmed, the programming destination address on the user MAT must
be passed to the programming program in which the program data is downloaded.
1. The start address of the programming destination on the user MAT must be stored in a general
register ER1. This parameter is called as flash multipurpose address area parameter (FMPAR).
Since the program data is always in units of 128 bytes, the lower eight bits (A7 to A0) must be
H'00 or H'80 as the boundary of the programming start address on the user MAT.
2. The program data for the user MAT must be prepared in the consecutive area. The program
data must be in the consecutive space which can be accessed by using the MOV.B instruction
of the CPU and in other than the flash memory space.
When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be
prepared by filling with the dummy code H'FF.
The start address of the area in which the prepared program data is stored must be stored in a
general register ER0. This parameter is called as flash multipurpose data destination area
parameter (FMPDR).
For details on the program processing procedure, see section 20.4.2, User Program Mode.
Rev. 3.00, 03/04, page 632 of 830