HD64F2168 Datasheet, PDF (834/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

25.3.3 Bus Timing
Table 25.8 shows the bus timing. In subclock (φSUB = 32.768 kHz) operation, external expansion
mode operation cannot be guaranteed.
Table 25.8 Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item
Address delay time
Address setup time
Address hold time
Symbol
t
AD
t
AS
t
AH
CS delay time (IOS,
t_CSD
CS256, CPCS1)
AS delay time
t_ASD
RD delay time 1
t_RSD1
RD delay time 2
t
RSD2
Read data setup time t
RDS
Read data hold time
t
RDH
Read data access time 1 t
ACC1
Read data access time 2 t_ACC2
Read data access time 3 t_ACC3
Read data access time 4 t_ACC4
Read data access time 5
WR delay time 1
WR delay time 2
WR pulse width 1
t_ACC5
t_WRD1
t
WRD2
t
WSW1
WR pulse width 2
t
WSW2
Write data delay time
t_WDD
Write data setup time
t_WDS
Write data hold time
t_WDH
WAIT setup time
t_WTS
WAIT hold time
t
WTH
Min.
Max.

15
0.5
×
t
cyc
–15

0.5
×
t
cyc
–

10

15
Unit
ns

15

15

15
15

0


1.0
×
t
cyc
–
30

1.5 × t_cyc – 25

2.0 × t_cyc – 30

2.5 × t_cyc – 25

3.0 × t_cyc – 30

15

15
1.0
×
t
cyc
–

20
1.5
×
t
cyc
–

20

25
0

0.5 × t_cyc – 5 
25

5

Test Conditions
Figures 25.12 to 25.16
Rev. 3.00, 03/04, page 794 of 830