HD64F2168 Datasheet, PDF (176/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

(2) 8-Bit, 3-State Data Access Space: Figure 6.15 shows the bus timing for an 8-bit, 3-state
access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used. Wait states can be inserted.
φ
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Read Cycle
Address
Data
T₁ T_AW T₂
T₃
T₄ T_DSW T₅
Write Cycle
Address
Data
T₁ T_AW T₂
T₃
T₄ T_DSW T₅
Address
Data
Address
Data
Figure 6.15 Bus Timing for 8-Bit, 3-State Access Space
(3) 16-Bit, 2-State Data Access Space: Figures 6.16 to 6.21 show bus timings for a 16-bit, 2-state
access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states
cannot be inserted.
Rev. 3.00, 03/04, page 136 of 830