HD64F2168 Datasheet, PDF (513/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Master transmit mode
Master receive mode
SCL
(master output)
9
SDA
A
(slave output)
SDA
(master output)
IRIC
SCL is fixed low until ICDR is read
SCL is fixed low until ICDR is read
1
2
3
4
5
6
7
8
9
12
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3]
A
Bit 7 Bit 6
Data 2
IRTR
ICDRF
ICDRR
Undefined value
Data 1
User processing
[1] TRS cleared to 0
[1] IRIC clear
[2] ICDR read
(Dummy read)
[4] IRIC clear
[6] ICDR read
(Data 1)
Figure 15.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)
SCL
(master output) ⁷
8
SDA
(slave output)
SDA
(master output)
Bit 1 Bit 0
Data 2
SCL is fixed low until ICDR is read
Stop condition generation
SCL is fixed low until ICDR is read
9
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[3]
Data 3
[8]
A
A
IRIC
IRTR
ICDRF
ICDRR
Data 1
Data 2
Data 3
User processing [4] IRIC clear
[7] ICDR read
(Data 2)
[6] ACKB set to 1
[9] IRIC clear
[10] ICDR read
(Data 3)
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
Figure 15.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
Rev. 3.00, 03/04, page 473 of 830